Bending fatigue of chip scale package interconnects

被引：0

作者：

Shetty, S ^{[1
]}

Lehtinen, V ^{[1
]}

Dasgupta, A ^{[1
]}

Halkola, V ^{[1
]}

Reinikainen, T ^{[1
]}

机构：

[1] Univ Maryland, CALCE Elect Prod & Syst Ctr, College Pk, MD 20742 USA

来源：

PROCEEDINGS OF THE SEM IX INTERNATIONAL CONGRESS ON EXPERIMENTAL MECHANICS | 2000年

关键词：

D O I：

暂无

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

This study investigates the effect of quasi-static bending loads (strain rate = 0.05/s) on the reliability of 0.5mm pitch Chip Scale Package (CSP) interconnects when assembled on FR4 substrates. The substrates have rows of CSPs and are subjected to three-point bend loads. Overstress curvature limits are experimentally determined and used as curvature limits for cyclic bend tests. The test configuration is simulated using finite element modeling (FEM) and the total strain accumulated in the solder joints is observed. The Coffin-Manson model is used to predict the cycles to failure for the applied loading. Predicted durability is compared to experimental measurements. Finite element simulations are repeated for life cycle loading to predict acceleration factors and to estimate durability.

引用

页码：723 / 726

页数：4

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