Bending fatigue of chip scale package interconnects

被引：0

作者：

Shetty, S ^{[1
]}

Lehtinen, V ^{[1
]}

Dasgupta, A ^{[1
]}

Halkola, V ^{[1
]}

Reinikainen, T ^{[1
]}

机构：

[1] Univ Maryland, CALCE Elect Prod & Syst Ctr, College Pk, MD 20742 USA

来源：

PROCEEDINGS OF THE SEM IX INTERNATIONAL CONGRESS ON EXPERIMENTAL MECHANICS | 2000年

关键词：

D O I：

暂无

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

This study investigates the effect of quasi-static bending loads (strain rate = 0.05/s) on the reliability of 0.5mm pitch Chip Scale Package (CSP) interconnects when assembled on FR4 substrates. The substrates have rows of CSPs and are subjected to three-point bend loads. Overstress curvature limits are experimentally determined and used as curvature limits for cyclic bend tests. The test configuration is simulated using finite element modeling (FEM) and the total strain accumulated in the solder joints is observed. The Coffin-Manson model is used to predict the cycles to failure for the applied loading. Predicted durability is compared to experimental measurements. Finite element simulations are repeated for life cycle loading to predict acceleration factors and to estimate durability.

引用

页码：723 / 726

页数：4

共 50 条

[21] TIME-DOMAIN ELECTROMAGNETIC ANALYSIS OF INTERCONNECTS IN A COMPUTER CHIP PACKAGE
BECKER, WD
HARMS, PH
MITTRA, R
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1992, 40 (12) : 2155 - 2163
[22] Analysis and modeling of microstrip-to-coplanar flip chip package interconnects
Ghouz, HHM
El-Sharawy, EB
INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING, 2001, 11 (04) : 202 - 211
[23] High bandwidth interconnects via a novel chip-stack package
Beyne, E
SOLID STATE TECHNOLOGY, 2002, 45 (04) : S19 - +
[24] Chip Package Interaction with Cu Pillar Interconnects - Impact of Die Warpage
Boehme, Bjoern
Sy, Markel
Capecchi, Simone
Breuer, Dirk
Cheng, Ta-Chien
Goetze, Christian
Kuechenmeister, Frank
2019 22ND EUROPEAN MICROELECTRONICS AND PACKAGING CONFERENCE & EXHIBITION (EMPC), 2019,
[25] Eutectic solder flip chip technology for Chip Scale Package
Takubo, C
Hirano, N
Doi, K
Tazawa, H
Hosomi, E
Hiruta, Y
NINETEENTH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM - PROCEEDINGS, 1996 IEMT SYMPOSIUM, 1996, : 488 - 493
[26] New approach to fatigue testing of chip-level interconnects
Anon
Journal of Research of the National Institute of Standards and Technology, 2002, 107 (04)
[27] Chip-scale Photonic Interconnects for Reconfigurable Computing
Sharkawy, Ahmed
Ebil, Ozgenc
Zablocki, Mathew
Shi, Shouyuan
Prather, Dennis W.
PHOTONIC AND PHONONIC CRYSTAL MATERIALS AND DEVICES X, 2010, 7609
[28] Metallic nanodevices for chip-scale optical interconnects
Tang, Liang
Miller, David A. B.
JOURNAL OF NANOPHOTONICS, 2009, 3
[29] Thermal analysis of a Chip Scale Package technology
Chambers, B
Lee, TYT
Blood, W
48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 1407 - 1412
[30] Chip scale package for image sensor device
Chao, Yung-Ching
Liu, John
Lee, Yao-Jung
Liu, De-Shin
Wang, Jeff
Chen, Ching-Yang
Huang, Sam
Lu, Alex
ADVANCES IN ELECTRONIC PACKAGING 2005, PTS A-C, 2005, : 993 - 998

← 1 2 3 4 5 →