Performance Analysis of FinFET Using Various Gate Dielectrics

被引：0

作者：

Nesamani, I. Flavia Princess ^{[1
]}

Rijo, P. C. ^{[1
]}

Raveendran, Geethanjali ^{[1
]}

Prabha, V. Lakshmi ^{[1
]}

机构：

[1] Karunya Univ Coimbatore, Govt Coll Teehnol, Coimbatore, Tamil Nadu, India

来源：

PROCEEDINGS OF 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2013) | 2013年

关键词：

DIBL; DG; SiO2; HfO2;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A Double Gate(DG) FinFET is designed in 30nm, 60nm technology with thickness of dielectric ranging from l. 2nm to 2.5nm and the observations are studied. Then DIBL of the device is calculated. The Double Gate(DG) FinFET is one of the promising devices to extend the CMOS technology beyond the scaling limit of conventional CMOS technology. DG FinFET has an excellent scalability and better short channel effect immunity compared to normal MOSFET device. High-k dielectric can be used in DG FinFET. While using the high-k dielectric it reduces the problems associated with gate leakage and increases the drain current. Sentaurus TCAD tool is used to find out the performance of the devices.

引用

页码：761 / 764

页数：4

共 50 条

[41] Design and Performance Analysis of Operational Transconductance Amplifier Using FinFET
Kumari, Amita
Singh, Balwinder
Pahuja, Hitesh
Jambagi, Suresh G.
Chhabra, Varun Aryan
PROCEEDINGS OF THE 8TH INTERNATIONAL CONFERENCE CONFLUENCE 2018 ON CLOUD COMPUTING, DATA SCIENCE AND ENGINEERING, 2018, : 544 - 549
[42] Analysis of gate dielectrics for SiC power UMOSFETS
Sridevan, S
Mclarty, PK
Baliga, BJ
ISPSD '97: 1997 IEEE INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, 1997, : 153 - 156
[43] TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance
Bhavya Kumar
Rishu Chaujar
Silicon, 2021, 13 : 3741 - 3753
[44] TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance
Kumar, Bhavya
Chaujar, Rishu
SILICON, 2021, 13 (10) : 3741 - 3753
[45] Subthreshold Performance Improvement of Underlapped FinFET Using Workfunction Modulated Dual-metal Gate Technique
Daga, Mitali
Mishra, Guru Prasad
SILICON, 2021, 13 (05) : 1541 - 1548
[46] Subthreshold Performance Improvement of Underlapped FinFET Using Workfunction Modulated Dual-metal Gate Technique
Mitali Daga
Guru Prasad Mishra
Silicon, 2021, 13 : 1541 - 1548
[47] Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance
Mridul Prakash Kashyap
Rishu Chaujar
Silicon, 2021, 13 : 3249 - 3256
[48] Novel Attributes and Analog Performance Analysis of Dual Material Gate FINFET Based High Sensitive Biosensors
Suguna, M.
Charumathi, V
Hemalatha, M.
Balamurugan, N. B.
Kumar, D. Sriram
Dhanaselvam, P. Suveetha
SILICON, 2022, 14 (05) : 2389 - 2396
[49] Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability
Patel, Kedar
Liu, Tsu-Jae King
Spanos, Costas J.
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (12) : 3055 - 3063
[50] A Split Gate Power FINFET With Improved ON-Resistance and Switching Performance
Luo, Xiaorong
Ma, Da
Tan, Qiao
Wei, Jie
Wu, Junfeng
Zhou, Kun
Sun, Tao
Liu, Qing
Zhang, Bo
Li, Zhaoji
IEEE ELECTRON DEVICE LETTERS, 2016, 37 (09) : 1185 - 1188

← 1 2 3 4 5 →