Performance Analysis of FinFET Using Various Gate Dielectrics

被引:0
|
作者
Nesamani, I. Flavia Princess [1 ]
Rijo, P. C. [1 ]
Raveendran, Geethanjali [1 ]
Prabha, V. Lakshmi [1 ]
机构
[1] Karunya Univ Coimbatore, Govt Coll Teehnol, Coimbatore, Tamil Nadu, India
关键词
DIBL; DG; SiO2; HfO2;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
A Double Gate(DG) FinFET is designed in 30nm, 60nm technology with thickness of dielectric ranging from l. 2nm to 2.5nm and the observations are studied. Then DIBL of the device is calculated. The Double Gate(DG) FinFET is one of the promising devices to extend the CMOS technology beyond the scaling limit of conventional CMOS technology. DG FinFET has an excellent scalability and better short channel effect immunity compared to normal MOSFET device. High-k dielectric can be used in DG FinFET. While using the high-k dielectric it reduces the problems associated with gate leakage and increases the drain current. Sentaurus TCAD tool is used to find out the performance of the devices.
引用
收藏
页码:761 / 764
页数:4
相关论文
共 50 条
  • [22] Performance Evaluation of Optimized Transistor Networks Built Using Independent-Gate FinFET
    Valdes, Andres M. A.
    Possani, Vinicius
    Marranghello, Felipe S.
    Reis, Andre I.
    Ribas, Renato P.
    2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2016, : 227 - 230
  • [23] Performance Analysis and Optimization of Under-Gate Dielectric Modulated Junctionless FinFET Biosensor
    Sehgal, Himani Dua
    Pratap, Yogesh
    Gupta, Mridula
    Kabra, Sneha
    IEEE SENSORS JOURNAL, 2021, 21 (17) : 18897 - 18904
  • [24] Simulation and Drain Current Performance analysis of High-K Gate Dielectric FinFET
    M. Aditya
    K. Srinivasa Rao
    K. Girija Sravani
    Koushik Guha
    Silicon, 2022, 14 : 4075 - 4078
  • [25] Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length
    Kaur, Navneet
    Gill, Sandeep Singh
    Kaur, Prabhjot
    SILICON, 2022, 14 (16) : 10989 - 11000
  • [26] Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length
    Navneet Kaur
    Sandeep Singh Gill
    Prabhjot Kaur
    Silicon, 2022, 14 : 10989 - 11000
  • [27] Simulation and Drain Current Performance analysis of High-K Gate Dielectric FinFET
    Aditya, M.
    Rao, K. Srinivasa
    Sravani, K. Girija
    Guha, Koushik
    SILICON, 2022, 14 (08) : 4075 - 4078
  • [28] Analysis and design of low power SRAM cell using independent gate FinFET
    Sikarwar V.
    Khandelwal S.
    Akashe S.
    Radioelectronics and Communications Systems, 2013, Allerton Press Incorporation (56) : 434 - 440
  • [29] Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment
    Park, Hong Bae
    Ju, Byongsun
    Kang, Chang Yong
    Park, Chanro
    Park, Chang Seo
    Lee, Byoung Hun
    Kim, Tea Wan
    Kim, Beom Seok
    Choi, Rino
    APPLIED PHYSICS LETTERS, 2009, 94 (04)
  • [30] RF Performance Enhancement in Underlap Tri-Gate FinFET
    Gupta, Shikhar
    Nandi, Ashutosh
    PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON INVENTIVE SYSTEMS AND CONTROL (ICISC 2018), 2018, : 760 - 762