A 32-bit RISC processor with concurrent error detection

被引：0

作者：

Maamar, A ^{[1
]}

Russell, G ^{[1
]}

机构：

[1] Univ Newcastle Upon Tyne, Dept Elect & Elect Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England

来源：

24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes the design and implementation of a 32-bit RISC Processor with a Concurrent Error Detection capability. The CED scheme uses Dong's Code where the error detection capability depends upon the number of checkbits used and not upon the number of data bits, hence can be made application specific. The equations used for check symbol prediction of both arithmetic and logical functions are outlined and its incorporation in a 32-bit Fault-Tolerant RISC processor described.

引用

页码：461 / 467

页数：3

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