32-bit RISC CPU Based on MIPS

被引：0
|
作者：
Yi, Kui [1 ]
Ding, Yue-Hua [1 ]
机构：
[1] WuHan Polytech Univ, Dept Comp Sci & Informat Engineer, Wuhan 430023, Hubei Province, Peoples R China
来源：
PROCEEDINGS OF THE 2009 SECOND PACIFIC-ASIA CONFERENCE ON WEB MINING AND WEB-BASED APPLICATION | 2009年
关键词：
MIPS; Data Flow; Data Path; Pipeline;
D O I：
10.1109/WMWA.2009.62
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully
引用
收藏
页码：124 / 128
页数：5
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