MIPS adds 16-/32-bit RISC ISA

被引:0
|
作者
Weiss, R
机构
来源
COMPUTER DESIGN | 1996年 / 35卷 / 12期
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:20 / 20
页数:1
相关论文
共 50 条
  • [1] PIRANHA BREAKS RISC MOLD WITH 16-/32-BIT CONTROLLERS
    不详
    [J]. COMPUTER DESIGN, 1994, 33 (13): : 82 - 82
  • [2] 32-bit RISC CPU Based on MIPS
    Yi, Kui
    Ding, Yue-Hua
    [J]. PROCEEDINGS OF THE 2009 SECOND PACIFIC-ASIA CONFERENCE ON WEB MINING AND WEB-BASED APPLICATION, 2009, : 124 - 128
  • [3] 16-/32-bit RISC tackles 68k embedded sockets
    Weiss, R
    [J]. COMPUTER DESIGN, 1996, 35 (10): : 69 - 72
  • [4] 32-BIT RISC CHIP RIPS THROUGH 5 MIPS
    OHR, S
    [J]. ELECTRONIC DESIGN, 1986, 34 (05) : 27 - 28
  • [5] Implementation of a 32-bit MIPS Based RISC Processor using Cadence
    Topiwala, Mohit N.
    Saraswathi, N.
    [J]. 2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 979 - 983
  • [6] Design and Implementation of 32-bit MIPS-Based RISC Processor
    Patra, Sumit
    Kumar, Sunil
    Verma, Swati
    Kumar, Arvind
    [J]. ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 747 - 757
  • [7] Software tool supports 16- and 32-bit code
    不详
    [J]. EE-EVALUATION ENGINEERING, 1996, 35 (08): : 96 - 96
  • [8] Instruction Decoder Module Design of 32-bit RISC CPU Based on MIPS
    Xiang YunZhu
    Ding YueHua
    [J]. SECOND INTERNATIONAL CONFERENCE ON GENETIC AND EVOLUTIONARY COMPUTING: WGEC 2008, PROCEEDINGS, 2008, : 347 - 351
  • [9] 32-bit RISC CPU Based on MIPS Instruction Fetch Module Design
    Yi, Kui
    Ding, Yue-Hua
    [J]. FIRST IITA INTERNATIONAL JOINT CONFERENCE ON ARTIFICIAL INTELLIGENCE, PROCEEDINGS, 2009, : 754 - 760
  • [10] Instruction Fetch Module Design of 32-bit RISC CPU Based on MIPS
    Ding, Yuehua
    Yi, Kui
    Sun, Ping
    [J]. DCABES 2008 PROCEEDINGS, VOLS I AND II, 2008, : 1109 - 1116