Design and Implementation of 32-bit MIPS-Based RISC Processor

With the continuously technology scaling, there exists a huge scope of undesirable hazards in processors. To solve the hazards, additional circuits are required in addition to conventional design and due to these additional circuits, the parameters area, power, and timing have been affected. Therefore, to make a processor having more number of operations without much affecting these parameters is a quite challenging task. In this paper, design and verification of 32-bit RISC CPU using 90 nm SCL CMOS technology is presented in detail. MIPS-based RISC architecture having operations like addition, subtraction, etc. Also having pipeline stages of five named as IF (Instruction Fetch), ID (Instruction Decode), EXE (Execute), MEM (Memory Access), WB (Write Back) to increase the throughput of the processor without degrading its latency. In this paper, all existing instructions as well as the new instructions, multiplication, and division are functionally verified. The analysis of performance parameters like area and power dissipation is done using synopsys design compiler with typical libraries of TSMC 90 nm technology.