Verification of a 32-bit RISC processor core

被引：1

作者：

Kasanko, T ^{[1
]}

Nurmi, J ^{[1
]}

机构：

[1] Tampere Univ Technol, Inst Digital & Comp Syst, FIN-33101 Tampere, Finland

来源：

2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/ISSOC.2004.1411161

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This paper presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.

引用

页码：107 / 110

页数：3

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