Implementation of a 32-bit MIPS Based RISC Processor using Cadence

This paper presents implementation of a 5-stage pipelined 32-bit High performance MIPS based RISC Core. MIPS (Microprocessor without Interlocked Pipeline Stages) is a RISC (Reduced Instruction Set Computer) architecture. A RISC is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. MIPS have 5 stages of pipeline viz. Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM) and Write Back (WB) modules. The various modules being used are Instruction Memory, Data Memory, ALU, Registers etc. The aim of this paper is to include Hazard detection unit and Data forwarding unit for efficient implementation of the pipeline. The design is developed using Verilog-HDL. The main goal is to do the complete ASIC flow (RTL to GDS II), using Cadence tool. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed using Cadence RTL complier using typical libraries of tsmc 0.18 urn technology.