A 32-bit RISC processor with concurrent error detection

被引：0
|
作者：
Maamar, A [1 ]
Russell, G [1 ]
机构：
[1] Univ Newcastle Upon Tyne, Dept Elect & Elect Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
来源：
24TH EUROMICRO CONFERENCE - PROCEEDING, VOLS 1 AND 2 | 1998年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper describes the design and implementation of a 32-bit RISC Processor with a Concurrent Error Detection capability. The CED scheme uses Dong's Code where the error detection capability depends upon the number of checkbits used and not upon the number of data bits, hence can be made application specific. The equations used for check symbol prediction of both arithmetic and logical functions are outlined and its incorporation in a 32-bit Fault-Tolerant RISC processor described.
引用
收藏
页码：461 / 467
页数：3
相关论文
共 50 条
  • [1] IMPLEMENTATION OF 32-BIT RISC PROCESSOR INCORPORATING HARDWARE CONCURRENT ERROR-DETECTION AND CORRECTION
    ELLIOTT, ID
    SAYERS, IL
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1990, 137 (01): : 88 - 102
  • [2] Verification of a 32-bit RISC processor core
    Kasanko, T
    Nurmi, J
    [J]. 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2004, : 107 - 110
  • [3] Design of 32-bit RISC processor and efficient verification
    Jeong, GY
    Park, JS
    [J]. KORUS 2003: 7TH KOREA-RUSSIA INTERNATIONAL SYMPOSIUM ON SCIENCE AND TECHNOLOGY, VOL 2, PROCEEDINGS: ELECTRICAL ENGINEERING AND INFORMATION TECHNOLOGY, 2003, : 222 - 227
  • [4] 32-BIT RISC PROCESSOR EXECUTES AT FULL THROTTLE
    STOCKTON, JF
    FARRELL, JJ
    [J]. ELECTRONIC PRODUCTS MAGAZINE, 1986, 28 (24): : 44 - 51
  • [5] INTEGER AND CONTROL UNITS FOR A GAAS 32-BIT RISC PROCESSOR
    CARBALLO, PP
    SARMIENTO, R
    NUNEZ, A
    [J]. MICROPROCESSING AND MICROPROGRAMMING, 1993, 37 (1-5): : 105 - 108
  • [6] Implementation of a 32-bit MIPS Based RISC Processor using Cadence
    Topiwala, Mohit N.
    Saraswathi, N.
    [J]. 2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 979 - 983
  • [7] Design and Implementation of 32-bit MIPS-Based RISC Processor
    Patra, Sumit
    Kumar, Sunil
    Verma, Swati
    Kumar, Arvind
    [J]. ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 747 - 757
  • [8] ODALRISC: A Small, Low Power, and Configurable 32-bit RISC Processor
    Lee, Imyong
    Lee, Dongwook
    Choi, Kiyoung
    [J]. ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 666 - 667
  • [9] 32-bit RISC Processor with Floating Point Unit for DSP Applications
    Palekar, Sangeeta
    Narkhede, Nitin
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 2062 - 2066
  • [10] Evaluation of a 32-bit microprocessor with built-in concurrent error-detection
    Gaisler, J
    [J]. TWENTY-SEVENTH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, DIGEST OF PAPERS, 1997, : 42 - 46
12345