SHA-3 Instruction Set Extension for A 32-bit RISC Processor Architecture

被引：0

作者：

Eissa, Ahmed S. ^{[1
]}

Elmohr, Mahmoud A. ^{[1
]}

Saleh, Mostafa A. ^{[1
]}

Ahmed, Khaled E. ^{[1
]}

Farag, Mohammed M. ^{[1
]}

机构：

[1] Univ Alexandria, Fac Engn, Dept Elect Engn, Alexandria, Egypt

来源：

2016 IEEE 27TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP) | 2016年

关键词：

SHA-3; Instruction Set Extension; Application-Specific Instruction Set Processor; MIPS; RISC;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Secure Hash Algorithm 3 (SHA-3) is a crypto-graphic hash function widely used in most security applications. The execution of the SHA-3 function is computationally intensive on lightweight embedded RISC processors. In this work, we advance a SHA-3 Instruction Set Extension (ISE) to improve its performance on a 32-bit MIPS processor. Two ISE approaches are proposed, namely native datapath and coprocessor-based ISEs. The ISE is developed with the aid of Codasip Studio, and the extended processor is implemented and benchmarked on a Xilinx Virtex-6-XC6VLX75t FPGA. The benchmarking results exhibit a 21% and 43% increase in the execution speed of the SHA-3 algorithm on the MIPS processor at the expense of 9% and 26% resource overheads for the native datapath and coprocessor-based ISEs, respectively.

引用

页码：233 / 234

页数：2

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