3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)

被引：10
|
作者：
Yang, Xiaoqiao [1 ]
Sun, Yabin [1 ]
Liu, Ziyu [2 ]
Liu, Yun [1 ]
Li, Xiaojin [1 ]
Shi, Yanling [1 ]
机构：
[1] East China Normal Univ, Dept Elect Engn, Shanghai Key Lab Multidimens Informat Proc, Shanghai 200241, Peoples R China
[2] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2022年 / 69卷 / 11期
基金：
中国国家自然科学基金; 上海市自然科学基金;
关键词：
Capacitance; Logic gates; Integrated circuit modeling; Dielectrics; Parasitic capacitance; Field effect transistors; Capacitors; Complementary FET (CFET); conformal mapping; fringe capacitance; parasitic capacitance; CMOS;
D O I：
10.1109/TED.2022.3207974
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work, an analytical model for fringe gate capacitance in complementary FET (CFET) is proposed. Three kinds of CFET based on the fin, gate-all-around (GAA) nanowire, and nanosheet are investigated. The fringe capacitance of CFET is separated into n-and p-FETs like dc performance. For each n-or p-FET, the fringe capacitances are divided into seven components according to the geometric topology. Conformal mapping and integral methods are used to calculate the dual-k dielectric perpendicular capacitance and coplanar plate capacitance. The model accuracy is verified with the 3-D field solver. The impact of device parameters on the overall fringe gate capacitance is also evaluated. The proposed fringe gate capacitance model is implanted in the BSIM model and is verified for 3-D TCAD simulations. The proposed model is helpful for reducing the parasitic capacitance in CFET device design and CFET-based circuit design.
引用
收藏
页码：5978 / 5984
页数：7
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