3-D Modeling of Fringe Gate Capacitance in Complementary FET (CFET)

被引：10
|
作者：
Yang, Xiaoqiao [1 ]
Sun, Yabin [1 ]
Liu, Ziyu [2 ]
Liu, Yun [1 ]
Li, Xiaojin [1 ]
Shi, Yanling [1 ]
机构：
[1] East China Normal Univ, Dept Elect Engn, Shanghai Key Lab Multidimens Informat Proc, Shanghai 200241, Peoples R China
[2] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2022年 / 69卷 / 11期
基金：
中国国家自然科学基金; 上海市自然科学基金;
关键词：
Capacitance; Logic gates; Integrated circuit modeling; Dielectrics; Parasitic capacitance; Field effect transistors; Capacitors; Complementary FET (CFET); conformal mapping; fringe capacitance; parasitic capacitance; CMOS;
D O I：
10.1109/TED.2022.3207974
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this work, an analytical model for fringe gate capacitance in complementary FET (CFET) is proposed. Three kinds of CFET based on the fin, gate-all-around (GAA) nanowire, and nanosheet are investigated. The fringe capacitance of CFET is separated into n-and p-FETs like dc performance. For each n-or p-FET, the fringe capacitances are divided into seven components according to the geometric topology. Conformal mapping and integral methods are used to calculate the dual-k dielectric perpendicular capacitance and coplanar plate capacitance. The model accuracy is verified with the 3-D field solver. The impact of device parameters on the overall fringe gate capacitance is also evaluated. The proposed fringe gate capacitance model is implanted in the BSIM model and is verified for 3-D TCAD simulations. The proposed model is helpful for reducing the parasitic capacitance in CFET device design and CFET-based circuit design.
引用
收藏
页码：5978 / 5984
页数：7
相关论文
共 50 条
  • [21] Modeling and significance of fringe capacitance in nonclassical CMOS devices with gate-source/drain underlap
    Kim, Seung-Hwan
    Fossum, Jerry G.
    Yang, Ji-Woon
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) : 2143 - 2150
  • [22] Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
    Park, Eunbin
    Song, Taigon
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 31 (02) : 177 - 187
  • [23] 3-D modeling
    McHugh, Randy
    Printed Circuit Design, 1998, 15 (02):
  • [24] HYDRODYNAMICS IN VESSELS STIRRED WITH ANCHORS AND GATE AGITATORS - NECESSITY OF A 3-D MODELING
    ABID, M
    XUEREB, C
    BERTRAND, J
    CHEMICAL ENGINEERING RESEARCH & DESIGN, 1992, 70 (A4): : 377 - 384
  • [25] 3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM
    Baig, Md. Aftab
    Yeh, Cheng-Jui
    Chang, Shu-Wei
    Qiu, Bo-Han
    Huang, Xiao-Shan
    Tsai, Cheng-Hsien
    Chang, Yu-Ming
    Sung, Po-Jung
    Su, Chun-Jung
    Cho, Ta-Chun
    De, Sourav
    Lu, Darsen
    Lee, Yao-Jen
    Lee, Wen-Hsi
    Wu, Wen-Fa
    Yeh, Wen-Kuan
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2023, 11 : 107 - 113
  • [26] A statistical algorithm for 3-D capacitance extraction
    Brambilla, A
    Maffezzoni, P
    IEEE MICROWAVE AND GUIDED WAVE LETTERS, 2000, 10 (08): : 304 - 306
  • [27] TSV Capacitance Aware 3-D Floorplanning
    Ahmed, Mohammad A.
    Chrzanowska-Jeske, M.
    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [28] PEEC capacitance extraction of 3-D interconnects
    Antonini, G.
    IET SCIENCE MEASUREMENT & TECHNOLOGY, 2007, 1 (04) : 201 - 209
  • [29] A NEW TECHNIQUE FOR MEASURING COUPLING-COEFFICIENTS AND 3-D CAPACITANCE CHARACTERIZATION OF FLOATING-GATE DEVICES
    CHOI, WL
    KIM, DM
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (12) : 2337 - 2342
  • [30] 3-D Modeling and Application
    Pittard, Julian M.
    Parkin, E. Ross
    Corcoran, Michael F.
    Hamaguchi, Kenji
    Stevens, Ian R.
    HIGHLIGHTS OF ASTRONOMY, VOL 15, 2010, 15 : 380 - 380
12345