Non-Preemptive Test Scheduling for Network-on-Chip(NoC) Based Systems by Reusing NoC as TAM

被引：0

作者：

Mali, Goutam ^{[1
]}

Das, Suman ^{[1
]}

Rahaman, Hafizur ^{[1
]}

Giri, Chandan ^{[1
]}

机构：

[1] Bengal Engn & Sci Univ, Dept Informat Technol, Sibpur 711103, Howrah, India

来源：

PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) | 2010年

关键词：

Network-on-Chip; test scheduling; test access mechanism;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Network-on-Chip (NoC) is becoming a promising communication architecture for the next generation embedded cores based system chips. The reuse of NoC as test access mechanism (TAM) for the embedded cores reduces the test time of the system. However, NoC reuse is limited by the on-chip routing resources and some other constraints. Therefore, efficient test scheduling methods are required to provide feasible test time, opening with other constraints. In this paper we have proposed the non-preemptive test scheduling approach based on Genetic Algorithm (GA) formulation. Experimental results with the ITC'02 System-on-Chip(SOC) test benchmarks show that GA produces scheduling of cores with 33% lesser overall test time of the system compared to the method proposed in the literature.

引用

页码：268 / 271

页数：4

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