Transient Error Management for Partially Adaptive Router in Network-on-Chip (NoC)

We propose a concatenate error detection method that exploits inherent information redundancy in network-on-chip (NoC) router, to address transient route computation errors. In our previous works, inherent information redundancy has been successfully employed to management transient errors in routers using XY deterministic routing algorithm. To prevent misrouting caused by transient errors injected in the partially adaptive router, we improve our previous method by using concatenate error detection logic. The proposed method is applied to a recent partially adaptive router based on logic-based distributed routing (LBDR). Analysis and simulation results show that the proposed method reduces the residual error rate by up to 1.98x and 3.47x over our previous approach and triple modular redundancy (TMR), respectively. More importantly, the proposed method consumes 2.6x less area and 2.1x less power consumption compared to TMR.