3D(Dimensional)-Wired and Wireless Network-on-Chip (NoC)

被引:5
|
作者
Ashokkumar, N. [1 ]
Nagarajan, P. [1 ]
Venkatramana, P. [1 ]
机构
[1] Sree Vidyanikethan Engn Coll, Ctr VLSI & Embedded Syst, Dept Elect & Commun Engn, Tirupati, Andhra Pradesh, India
关键词
3D NoC (3Dimensional Network-on-Chip); TSV (Through silicon via); Wired and wireless NoC; Topology; COMPRESSION;
D O I
10.1007/978-981-15-0146-3_12
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Network on Chip is a special unique case of parallel computing systems defined by the tight constraints such as availability of resources, area, cost of the NoC architecture and power consumption. NoC is designed with three main components: switches, Network Interfaces (NIs) and links. NoC is used for several application domains, such as multi-media processing, consumer electronics, biological applications, etc. NoC is the technology proposed to solve the shortcoming of buses. This technique is used to design communication subsystem among IP cores (Intellectual property core) in a SoC design. In this chapter, we have discussed about 3D integrated circuits, 3D wired and wireless NoC, Emerging Technologies, and Literature Survey.
引用
收藏
页码:113 / 119
页数:7
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