Performance Analysis of the Impact of Design Parameters to Network-on-Chip (NoC) Architecture

Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a solution to System-on-Chip (SoC). The routing algorithm and topology are significant because it powerfully affects the overall performance of Network-on-Chip (NoC). Routing algorithm can classify into partial-adaptive, fully adaptive and deterministic. In this project, some parameter has evaluated to study the impact of parameter towards NoC performance. The Noxim and NIRGAM simulator are used to observe the performance of each routing algorithm and topology. The experiment showed that the network size and packet injection is proportional to the average latency, throughput, and energy. Torus topology has better performance compare to mesh topology. From the experiment 1 and 2 results, we observe that, although adaptive routing algorithm has better performance in 4 x 4 mesh topology but deterministic routing algorithm showed a better performance in the 9 x 9 mesh topology.