Implementation of a DC Compact Model for Double-Gate Tunnel-FET Based on 2D Calculations and Application in Circuit Simulation

被引：0

作者：

Horst, Fabian ^{[1
,2
]}

Graef, Michael ^{[1
,2
]}

Hosenfeld, Fabian ^{[1
,2
]}

Farokhnejad, Atieh ^{[1
,2
]}

Hain, Franziska ^{[1
,2
]}

Gia Vinh Luong ^{[3
,4
]}

Zhao, Qing-Tai ^{[3
,4
]}

Iniguez, Benjamin ^{[2
]}

Kloes, Alexander ^{[1
]}

机构：

[1] Tech Hsch Mittelhessen, Competence Ctr Nanotechnol & Photon, Giessen, Germany

[2] Univ Rovira & Virgili, DEEEA, Tarragona, Spain

[3] Peter Grunberg Inst PGI 9 IT, Julich, Germany

[4] JARA FIT Forschungszentrum Julich, Julich, Germany

来源：

2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2016年

关键词：

Compact modeling; Verilog-A; Double-Gate (DG) Tunnel-FET; Nanowire GAA Tunnel-FET; Circuit simulation; ELECTROSTATICS; LOGIC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a two-dimensional physics-based compact model for a double-gate (DG) Tunnel-FET (TFET) implemented in Verilog-A. The compact model is derived from an analytical model published in [1], [2], [3]. TCAD Sentaurus simulation data as well as measurement data are used to verify and show the flexibility of the modeling approach. Advantages and limitations of the compact model are analyzed and discussed. In order to demonstrate the numerical stability of the model, a basic circuit in form of a single stage inverter is simulated using complementary Tunnel-FET logic. The results of this circuit simulation are compared to measurements on fabricated inverters and are in good agreement.

引用

页码：456 / 459

页数：4

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