Implementation of a DC Compact Model for Double-Gate Tunnel-FET Based on 2D Calculations and Application in Circuit Simulation

被引：0

作者：

Horst, Fabian ^{[1
,2
]}

Graef, Michael ^{[1
,2
]}

Hosenfeld, Fabian ^{[1
,2
]}

Farokhnejad, Atieh ^{[1
,2
]}

Hain, Franziska ^{[1
,2
]}

Gia Vinh Luong ^{[3
,4
]}

Zhao, Qing-Tai ^{[3
,4
]}

Iniguez, Benjamin ^{[2
]}

Kloes, Alexander ^{[1
]}

机构：

[1] Tech Hsch Mittelhessen, Competence Ctr Nanotechnol & Photon, Giessen, Germany

[2] Univ Rovira & Virgili, DEEEA, Tarragona, Spain

[3] Peter Grunberg Inst PGI 9 IT, Julich, Germany

[4] JARA FIT Forschungszentrum Julich, Julich, Germany

来源：

2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2016年

关键词：

Compact modeling; Verilog-A; Double-Gate (DG) Tunnel-FET; Nanowire GAA Tunnel-FET; Circuit simulation; ELECTROSTATICS; LOGIC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a two-dimensional physics-based compact model for a double-gate (DG) Tunnel-FET (TFET) implemented in Verilog-A. The compact model is derived from an analytical model published in [1], [2], [3]. TCAD Sentaurus simulation data as well as measurement data are used to verify and show the flexibility of the modeling approach. Advantages and limitations of the compact model are analyzed and discussed. In order to demonstrate the numerical stability of the model, a basic circuit in form of a single stage inverter is simulated using complementary Tunnel-FET logic. The results of this circuit simulation are compared to measurements on fabricated inverters and are in good agreement.

引用

页码：456 / 459

页数：4

共 50 条

[21] Self-consistent 2D compact model for nanoscale double gate MOSFETs
Kolberg, S.
Fjeldly, T. A.
Iniguez, B.
[J]. COMPUTATIONAL SCIENCE - ICCS 2006, PT 4, PROCEEDINGS, 2006, 3994 : 607 - 614
[22] Surface Orientated < 100 > , < 110 > , and < 111 > Silicon-based Double-Gate Tunnel-FET for Linearity and Analog/RF Performance Analysis
Maurya, Ashish
Koley, Kalyan
Kumar, Pankaj
Kumar, Jitendra
[J]. SILICON, 2023, 15 (09) : 3829 - 3839
[23] A 2-D semi-analytical model of double-gate tunnel field-effect transistor
许会芳
代月花
李宁
徐建斌
[J]. Journal of Semiconductors, 2015, 36 (05) - 34
[24] A 2-D semi-analytical model of double-gate tunnel field-effect transistor
Xu Huifang
Dai Yuehua
Li Ning
Xu Jianbin
[J]. JOURNAL OF SEMICONDUCTORS, 2015, 36 (05)
[25] Quantum simulation of a heterojunction vertical tunnel FET based on 2D transition metal dichalcogenides
Cao, Jiang
Cresti, Alessandro
Esseni, David
Pala, Marco
[J]. SOLID-STATE ELECTRONICS, 2016, 116 : 1 - 7
[26] A 2-D semi-analytical model of double-gate tunnel field-effect transistor
许会芳
代月花
李宁
徐建斌
[J]. Journal of Semiconductors, 2015, (05) : 28 - 34
[27] A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance
Dash, S.
Mishra, G. P.
[J]. ADVANCES IN NATURAL SCIENCES-NANOSCIENCE AND NANOTECHNOLOGY, 2015, 6 (03)
[28] 2D quantum mechanical device modeling and simulation: Centre-channel (CC) and double-gate (DG) MOSFET
Kim, KD
Won, TY
[J]. MOLECULAR SIMULATION, 2005, 31 (12) : 825 - 830
[29] Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET
Paul, Dip Joti
Abdullah-Al-Kaiser, Md.
Islam, Md. Shofiqul
Khosru, Quazi D. M.
[J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2018, 17 (04) : 1567 - 1577
[30] Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET
Dip Joti Paul
Md. Abdullah-Al-Kaiser
Md. Shofiqul Islam
Quazi D. M. Khosru
[J]. Journal of Computational Electronics, 2018, 17 : 1567 - 1577

← 1 2 3 4 5 →