Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

A physically based model of the double-gate juntionless transistor which is capable of describing accumulation and depletion regions is implemented in Verilog-A in order to perform DC circuit simulations. Analytical description of the difference of potentials between the center and the surface of the silicon layer allows the determination of the mobile charges. Furthermore, mobility degradation, series resistance, as well as threshold voltage roll-off, drain saturation voltage, channel shortening and velocity saturation are also considered. In order to provide this model to all of the community, the implementation of this model is performed in Ngspice, which is a free circuit simulation with an ADMS interface to integrate Verilog-A models. Validation of the model implementation is done through 2D numerical simulations of transistors with 1 mu m and 40 nm silicon channel length and 1 x 10(19) or 5 x 10(18) cm(-3) doping concentration of the silicon layer with 10 and 15 nm silicon thickness. Good agreement between the numerical simulated behavior and model implementation is obtained, where only eight model parameters are used.