Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model

被引：0
|
作者：
Moreira, Claudio V. [1 ]
Trevisoli, Renan [2 ]
Pavanello, Marcelo Antonio [1 ]
机构：
[1] Ctr Univ FEI, Ave Humberto AC Branco 3972, BR-09850901 Sao Bernardo Do Campo, Brazil
[2] Univ Fed ABC, Sao Bernardo Do Campo, Brazil
来源：
2019 LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC) | 2019年
基金：
巴西圣保罗研究基金会;
关键词：
Junctionless Transistor; SPICE; Verilog-A;
D O I：
10.1109/laed.2019.8714741
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents the results of static and dynamic compact model of trigate junctionless nanowire transistor implementation in Verilog-A language to allow SPICE circuits simulations. The model implementation for n-type and p-type junctionless transistors has been compared with 3D Technology Computer-Aided Design (TCAD) simulations for several biases, doping concentrations, channel length and fin width, showing good agreement.
引用
收藏
页码：96 / 99
页数：4
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