Compact model for short-channel symmetric double-gate junctionless transistors

被引：19

作者：

Avila-Herrera, F. ^{[1
]}

Cerdeira, A. ^{[1
]}

Paz, B. C. ^{[2
]}

Estrada, M. ^{[1
]}

Iniguez, B. ^{[3
]}

Pavanello, M. A. ^{[2
]}

机构：

[1] CINVESTAV IPN, Dept Ingn Elect, Secc Elect Estado Solido, Mexico City 07360, DF, Mexico

[2] Ctr Univ FEI, Dept Elect Engn, BR-09850901 Sao Bernardo Do Campo, Brazil

[3] Univ Rovira & Virgili, Dept Engn Elect Elect & Automat, E-43007 Tarragona, Spain

来源：

SOLID-STATE ELECTRONICS | 2015年 / 111卷

基金：

巴西圣保罗研究基金会;

关键词：

Compact analytical model; Double-gate JLT; SCE model; JLT; THRESHOLD VOLTAGE; CORE MODEL; MOSFETS; BULK;

D O I：

10.1016/j.sse.2015.06.009

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 x 10(18) and 1 x 10(19) cm (3), as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：196 / 203

页数：8

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