A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET

被引:3
|
作者
Kaur, Sarabjeet [1 ]
Raman, Ashish [1 ]
Sarin, Rakesh Kumar [1 ]
机构
[1] Dr BR Ambedkar Natl Inst Technol, ECE Dept, VLSI Design Lab, Jalandhar, Punjab, India
关键词
Capacitance model; Charge model; Hetero-gate-dielectric; Tunnel field effect transistor (TFET);
D O I
10.1016/j.spmi.2020.106748
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
In this paper, a charge-based capacitance model has been proposed for a double-gate (DG) heterogate-dielectric tunnel FET (HGD-TFET). By solving the Poisson equation, the surface potential model is developed. The developed potential model is then used for developing the terminal capacitance model and drain current model. The device is working under enhancement-mode as the channel region is considered to be n-type doped. For developing the charge model, accumulated charges and ionized impurity charges are included in the channel charge equation. The developed model can capture the impact of V-G = 0 V and V-D = 0 V. The model can also successfully capture the scaling issues and gate dielectric variation. To ensure the performance of the developed model, the results are validated with TCAD simulation results and a good agreement is achieved between them. Since, high-k gate dielectric and low-k gate dielectric are used in a single structure, it combines the merit of both and hence, results in the performance improvement.
引用
收藏
页数:11
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