Accounting for Series Resistance in the Compact Model of Triple-Gate Junctionless Nanowire Transistors

被引：0
|
作者：
Trevisoli, Renan [1 ]
Doria, Rodrigo T. [2 ]
de Souza, Michelly [2 ]
Pavanello, Marcelo A. [2 ]
机构：
[1] Univ Fed ABC, UFABC, Santo Andre, Brazil
[2] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo, Brazil
来源：
2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO) | 2018年
基金：
巴西圣保罗研究基金会;
关键词：
Junctionless Transistors; Analytical Model; Series Resistance; Nanowires;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The aim of this work is to propose a method to account for the series resistance effect on the compact drain current model of Junctionless Nanowire Transistors. The model is validated through comparisons against iterative analysis and three-dimensional numerical simulations. The characteristics of the devices, i.e. the width, height, channel length, doping concentration and gate oxide thickness, have been varied in the analysis to demonstrate the model applicability.
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页数：4
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