ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC

被引：0
|
作者：
Dai, Chia-Tsen [1 ]
Ker, Ming-Dou [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan
来源：
2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2015年
关键词：
HOLDING-VOLTAGE; TECHNOLOGY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-mu m HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.
引用
收藏
页码：380 / 383
页数：4
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