Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection

被引：0

作者：

Liao, Seian-Feng ^{[1
]}

Tang, Kai-Neng ^{[1
]}

Ker, Ming-Dou ^{[1
]}

Yeh, Jia-Rong ^{[2
]}

Chiou, Hwa-Chyi ^{[2
]}

Huang, Yeh-Jen ^{[2
]}

Tsai, Chun-Chien ^{[2
]}

Jou, Yeh-Ning ^{[2
]}

Lin, Geeng-Lih ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan

[2] Vanguard Int Semicond Corp, Hsinchu, Taiwan

来源：

2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD) | 2015年

关键词：

DESIGN; LDMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-mu m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

引用

页码：185 / 188

页数：4

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