Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes

被引：16
|
作者：
Ker, Ming-Dou [1 ,2 ]
Wang, Chang-Tzu [1 ]
机构：
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
[2] I Shou Univ, Dept Elect Engn, Kaohsiung 84001, Taiwan
来源：
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2009年 / 9卷 / 01期
关键词：
Electrostatic discharge (ESD); low-voltage CMOS; mixed-voltage I/O; substrate-triggered technique;
D O I：
10.1109/TDMR.2008.2008639
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Two new electrostatic discharge (ESD) protection design by using only 1 x VDD low-voltage devices for mixed-voltage I/O buffer with 3 x VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13-mu m 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.
引用
收藏
页码：49 / 58
页数：10
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