Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator

被引：0
|
作者：
Luo, Zhicong [1 ,2 ]
Ker, Ming-Dou [1 ]
机构：
[1] Natl Chiao Tung Univ, Biomed Elect Translat Res Ctr, Hsinchu, Taiwan
[2] Fujian Agr & Forestry Univ, Coll Mech & Elect Engn, Fuzhou, Fujian, Peoples R China
来源：
2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-mu m CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (V-DD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the coupling capacitors and the cross-coupled transistor pairs. Electrical overstress and the gate-oxide reliability issues can be fully eliminated because all transistors in the proposed level shifter are operating within the safe voltage range.
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页数：4
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