SOI-DRAM circuit technologies: For low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield, The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic, The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled legit also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure, A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.