Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers

Hard multiple generation is the bottleneck operation in radix-8 Booth encoded modulo 2(n)-1 and modulo 2(n)+1 multipliers. In this paper, fast hard multiple generators for the moduli 2(n)-1 and 2(n)+1 are proposed. They are implemented as parallel-prefix structures based on the simplified carry equations. Synthesis results based on TSMC 0.18 mu m, 1.8V CMOS standard-cell library show that the proposed modulo 2(n)-1 hard multiple generator reduces the critical path delay of the fastest general-purpose modulo 2(n)-1 adder by 12% and 10% for n = 8 and n = 64, respectively. Compared to the smallest modulo 2(n)-1 adder, the proposed design leads to 19% and 12% savings in silicon area for n = 8 and n = 64, respectively. The proposed modulo 2(n)+1 hard multiple generator also has the least critical path delay among the existing modulo 2(n)+1 adders.