Efficient Modulo 2n+1 Multipliers

被引：13

作者：

Chen, Jian Wen ^{[1
]}

Yao, Ruo He ^{[1
]}

Wu, Wei Jing ^{[1
]}

机构：

[1] S China Univ Technol, Sch Elect & Informat Engn, Guangzhou 510640, Guangdong, Peoples R China

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 12期

关键词：

Diminished-1; representation; modular arithmetic; modular multiplier; VLSI IMPLEMENTATION; MULTIPLICATION; ARCHITECTURE; DESIGN;

D O I：

10.1109/TVLSI.2010.2080330

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Area-time efficient modulo (2(n) + 1) multipliers are proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished-1. By using the radix-4 Booth recoding, the new multipliers reduce the number of the partial products to n/2 for even and (n + 1)/2 for n odd except for one correction term. Although one correction term is used, the circuit is very simple. The architecture for the new multipliers consists of an inverted end-around-carry carry save adder tree and one diminished-1 adder. The new multipliers receive full inputs and avoid (n + 1)-bit circuits. The analytical and experimental results indicate that the new multipliers offer enhanced operation speed and more compact area among all the efficient existing solutions.

引用

页码：2149 / 2157

页数：9

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