Efficient modulo 2N+1 tree multipliers for diminished-1 operands

被引：0

作者：

Efstathiou, C ^{[1
]}

Vergos, HT ^{[1
]}

Dimitrakopoulos, G ^{[1
]}

Nikolos, D ^{[1
]}

机构：

[1] TEI Athens, Dept Informat, Athens 12210, Greece

来源：

ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work we propose a new method for designing modulo 2(n)+1 multipliers for diminished-1 operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.

引用

页码：200 / 203

页数：4

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