Efficient modulo 2n+1 multipliers for diminished-1 representation

An efficient architecture for diminished-1 modulo (2(n) + 1) multipliers is described. The new architecture is built using a pure radix-4 Booth recoding block, an inverted end-around-carry carry save adder tree and a final diminished-1 adder. Although one correction term is used, the complexity of the circuit is very simple. There are n/2 partial products (PP), one simple correction term and one constant, each one n bits wide. The new multipliers can handle zero inputs and results. The analytical and experimental results indicate that the new multipliers offer better speed and more compact than previously published solutions.