Novel modulo 2n+1 multipliers

被引：0
|
作者：
Vergos, H. T. [1 ]
Efstathiou, C. [2 ]
机构：
[1] Univ Patras, Comp Engn & Informat Dept, GR-26500 Patras, Greece
[2] TEI Athens, Dept Informat, GR-12210 Athens, Greece
来源：
DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new modulo 2(n) + 1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder The proposed architecture utilizes a total of (n + 1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder
引用
收藏
页码：168 / +
页数：2
相关论文
共 50 条
  • [1] Efficient Modulo 2n+1 Multipliers
    Chen, Jian Wen
    Yao, Ruo He
    Wu, Wei Jing
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (12) : 2149 - 2157
  • [2] Design of efficient modulo 2n+1 multipliers
    Vergos, H. T.
    Efstathiou, C.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (01): : 49 - 57
  • [3] Efficient diminished-1 modulo 2n+1 multipliers
    Efstathiou, C
    Vergos, HT
    Dimitrakopoulos, G
    Nikolos, D
    IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (04) : 491 - 496
  • [4] NOVEL MODULO 2n+1 SUBTRACTORS
    Vassalos, E.
    Bakalis, D.
    Vergos, H. T.
    2009 16TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, VOLS 1 AND 2, 2009, : 597 - +
  • [5] Efficient modulo 2n+1 multipliers for diminished-1 representation
    Chen, J. W.
    Yao, R. H.
    IET CIRCUITS DEVICES & SYSTEMS, 2010, 4 (04) : 291 - 300
  • [6] Novel Modulo 2n+1 Subtractor and Multiplier
    Younes, Dina
    Steffan, Pavel
    PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON SYSTEMS (ICONS 2011), 2011, : 36 - 38
  • [7] Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS
    Muralidharan, Ramya
    Chang, Chip-Hong
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (10) : 2263 - 2274
  • [8] Efficient modulo 2N+1 tree multipliers for diminished-1 operands
    Efstathiou, C
    Vergos, HT
    Dimitrakopoulos, G
    Nikolos, D
    ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 200 - 203
  • [9] Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers
    Muralidharan, Ramya
    Chang, Chip-Hong
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 717 - 720
  • [10] On Modulo 2n+1 Adder Design
    Vergos, Haridimos T.
    Dimitrakopoulos, Giorgos
    IEEE TRANSACTIONS ON COMPUTERS, 2012, 61 (02) : 173 - 186
12345