NOVEL MODULO 2n+1 SUBTRACTORS

被引：0

作者：

Vassalos, E. ^{[1
]}

Bakalis, D. ^{[1
]}

Vergos, H. T.

机构：

[1] Univ Patras, Dept Phys, Elect Lab, GR-26110 Patras, Greece

来源：

2009 16TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, VOLS 1 AND 2 | 2009年

关键词：

Residue number system; modulo 2(n)+1 circuits; subtraction; normal and diminished-one number representation; IMPLEMENTATION; ARCHITECTURE; DESIGN;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Novel architectures for designing modulo 2(n)+1 subtractors are introduced, for both the normal and the diminished-one number representation of the operands. Zero-handling is also considered in the diminished-one operand representation case. The modulo 2(n)+1 subtractors for operands in the normal representation that are proposed are shown to be more efficient in area, delay and power dissipation than the currently most efficient ones. The proposed diminished-one modulo 2(n)+1 subtractors offer similar characteristics to those of the corresponding diminished-one adders.

引用

页码：597 / +

页数：2

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