Fault characterizations and design-for-testability technique for detecting IDDQ faults in CMOS/BiCMOS circuits

被引：0
|
作者：
Raahemifar, K [1 ]
Ahmadi, M [1 ]
机构：
[1] Ryerson Polytech Univ, Dept Elect & Comp Engn, Toronto, ON M5B 2K3, Canada
来源：
CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING 2001, VOLS I AND II, CONFERENCE PROCEEDINGS | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause I-D DQ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.
引用
收藏
页码：1091 / 1098
页数：4
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