FAULT CHARACTERIZATION, TESTING CONSIDERATIONS, AND DESIGN FOR TESTABILITY OF BICMOS LOGIC-CIRCUITS

BiCMOS technology is one of the leading candidate technologies for future generations of high-speed VLSI circuits. It is of great importance to study the effect of physical failures on BiCMOS logic circuits and the effect of these failures on the testing techniques currently employed for MOS and bipolar technologies. This paper provides the results of a simulation-based fault characterization study of BiCMOS logic circuits. Based on the fault characterization results, we have studied different techniques for testing BiCMOS logic circuits. Moreover, we present a novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits.