FAULT CHARACTERIZATION, TESTING CONSIDERATIONS, AND DESIGN FOR TESTABILITY OF BICMOS LOGIC-CIRCUITS

被引：6

作者：

SALAMA, AE

ELMASRY, MI

机构：

[1] VLSI Research Group, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont.

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 06期

关键词：

D O I：

10.1109/4.135340

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

BiCMOS technology is one of the leading candidate technologies for future generations of high-speed VLSI circuits. It is of great importance to study the effect of physical failures on BiCMOS logic circuits and the effect of these failures on the testing techniques currently employed for MOS and bipolar technologies. This paper provides the results of a simulation-based fault characterization study of BiCMOS logic circuits. Based on the fault characterization results, we have studied different techniques for testing BiCMOS logic circuits. Moreover, we present a novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits.

引用

页码：944 / 947

页数：4

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