共 50 条
- [2] FAULT EFFECTS IN ASYNCHRONOUS SEQUENTIAL LOGIC-CIRCUITS [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1993, 140 (06): : 327 - 332
- [3] APPLICATION OF FAULT FOLDING IN TEST GENERATION FOR LOGIC-CIRCUITS [J]. DIGITAL PROCESSES, 1978, 4 (02): : 109 - 120
- [4] SET fault tolerant combinational circuits based on majority logic [J]. 21ST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2006, : 345 - +