On-line IDDQ fault testing for CMOS/BiCMOS logic families

被引：0
|
作者：
Raahemifar, K [1 ]
Ahmadi, M [1 ]
机构：
[1] Univ Windsor, Dept Elect Engn, Windsor, ON N9B 3P4, Canada
来源：
ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause I-DDQ faults, while open defects result in delay or stud-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.
引用
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页码：105 / 109
页数：5
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