Closed-Form Expressions for the Capacitance of Tapered Through-Silicon Vias

Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through silicon vias (TSVs) are proposed. The expressions are functions of the geometric and material parameters of TSVs. They also can be applied to the cylindrical TSVs when the slope angle is zero. The two parasitic capacitances increase as the slope angle increases, which implies that the tapered TSVs have larger capacitances compared with the cylindrical TSVs. Computer Simulation Technology Electromagnetic Studio (TM) (CST EMS) is used to verify the expressions. The results indicate the maximum errors between the expressions and simulation results for the insulator capacitance and the substrate capacitance are 6.27% and 4.15%, respectively.