Universal closed-form expression based on magnetic flux density for the inductance of Tapered Through-Silicon Vias (T-TSVs)

被引：3

作者：

Mei, Zheng ^{[1
]}

Dong, Gang ^{[1
]}

Yang, Yintang ^{[1
]}

Zheng, Junping ^{[1
]}

Chai, Jingrui ^{[1
]}

Zhu, Weijun ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China

来源：

MICROELECTRONICS JOURNAL | 2017年 / 63卷

基金：

中国国家自然科学基金;

关键词：

Three-dimensional (3D) integrated circuit (IC); Tapered through silicon vias (T-TSVs); Inductance; 3-D ICS; MODEL; IMPEDANCE; DESIGN; CAPACITANCE;

D O I：

10.1016/j.mejo.2017.02.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a universal closed-form expression for the parasitic inductance of tapered through-silicon vias (TTSVs) with a frequency of up to 20 GHz is proposed. The expression, which considers skin and proximity effects, can be used to calculate the self-partial inductance and mutual-partial inductance, considering TSVs located in adjacent layers or in the same layer. When the slope angle is 90 degrees, the obtained formulas can be reduced to the formulas of cylindrical TSVs. The comparison between the results of the proposed formulas and the results of the three-dimensional quasi-static field solver (Q3D) demonstrates that the proposed formulas are extremely accurate, with a maximum error of 2%.

引用

页码：20 / 26

页数：7

共 6 条

[1] Universal closed-form expressions for the inductance of tapered through silicon vias (T-TSVs) based on vector magnetic potential
Mei, Zheng
Dong, Gang
Yang, Yintang
Zheng, Junping
Zhao, Yingbo
Zhu, Weijun
[J]. IEICE ELECTRONICS EXPRESS, 2016, 13 (18):
[2] Closed-Form Expressions for the Capacitance of Tapered Through-Silicon Vias
Su, Jinrong
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Liang, Yuanjun
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[4] Closed-Form Expression for Capacitance of Tapered Through-Silicon-Vias Considering MOS Effect
Wang, Fengjuan
Yang, Yintang
Zhu, Zhangming
Liu, Xiaoxian
Zhang, Yan
[J]. 2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2013, : 1250 - 1254
[5] Closed-Form Expressions of Parasitic Parameters for Different Sidewall Roughness of Through-Silicon Vias Interconnects
Fang, Zhen
Zhang, Jihua
Gao, Libin
Li, Shuqi
Liu, Jinxu
Chen, Hongwei
Yang, Xiaolin
Li, Wenlei
Cai, Xingzhou
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (02) : 1160 - 1165
[6] Inductance of Different Profiles of Through Glass Vias based on magnetic flux density
Liu, Yang
Zhu, Zhangming
Ding, Ruixue
Liu, Xiaoxian
Lu, Qijun
Yin, Xiangkun
Yang, Yintang
[J]. 2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018), 2018, : 439 - 442

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