Closed-Form Expression for Capacitance of Tapered Through-Silicon-Vias Considering MOS Effect

被引：0
|
作者：
Wang, Fengjuan [1 ]
Yang, Yintang [1 ]
Zhu, Zhangming [1 ]
Liu, Xiaoxian [1 ]
Zhang, Yan [1 ]
机构：
[1] Xidian Univ, Sch Microelect, Xian, Peoples R China
来源：
2013 14TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT) | 2013年
关键词：
Tapered TSV; Parasitic Capacitance; MOS Effect; Poisson's Equation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, closed-form expression of the parasitic capacitance of the tapered Through-Silicon Via (TSV) is proposed, which also cover the cylindrical TSV when the slop wall angle is 90 degrees. The comparison between the results of Ansoft Q3D verification and Matlab calculation are made. It shows that the root mean square error is less than 6.10%, over a wide range of the bottom radius and the height of tapered TSV, and the oxide thickness, therefore, the expression presented proves to be accurate.
引用
收藏
页码：1250 / 1254
页数：5
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