Universal closed-form expressions for the inductance of tapered through silicon vias (T-TSVs) based on vector magnetic potential

被引：1

作者：

Mei, Zheng ^{[1
]}

Dong, Gang ^{[1
]}

Yang, Yintang ^{[1
]}

Zheng, Junping ^{[1
]}

Zhao, Yingbo ^{[2
,3
]}

Zhu, Weijun ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian, Peoples R China

[2] South Taibai Rd, Xian 710071, Peoples R China

[3] Xian Univ Architecture & Technol, 13 Yanta Rd, Xian 710055, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2016年 / 13卷 / 18期

基金：

中国国家自然科学基金;

关键词：

three-dimensional integrated circuits (3D ICs); tapered through silicon vias (T-TSVs); inductance; vector magnetic potential; 3-D; CAPACITANCE; IMPEDANCE; MODEL;

D O I：

10.1587/elex.13.20160621

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes novel formulas for the calculation of the parasitic inductance of Tapered-Through Silicon Vias (T-TSVs), considering the TSVs located in adjacent layers. The formulas can not only be reduced to calculate the self-partial inductance and mutual-partial inductance of T-TSVs located in the same layer but also be used for cylindrical TSVs when the slope angle is 90 degrees. The comparison between the results of the proposed formulas and Ansoft Q3D shows that the proposed formulas have very high accuracy with a maximum error of 2.5%.

引用

页数：9

共 7 条

[1] Universal closed-form expression based on magnetic flux density for the inductance of Tapered Through-Silicon Vias (T-TSVs)
Mei, Zheng
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[5] Closed-Form Expressions of Parasitic Parameters for Different Sidewall Roughness of Through-Silicon Vias Interconnects
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[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (02) : 1160 - 1165
[6] Frequency-dependent closed-form expressions for inductance and resistance of a single interconnect on a silicon substrate
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[7] Closed-form Expressions of Vector Magnetic and Magnetic Gradient Tensor due to a Line Segment
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