Closed-Form Expressions of Parasitic Parameters for Different Sidewall Roughness of Through-Silicon Vias Interconnects

The sidewall roughness of through-silicon vias (TSVs) plays a critical role in the reliability and integrity of signal transmission, particularly at high frequencies. In this study, we introduce a novel approach utilizing generalized closed-form expressions to assess the parasitic RLGC parameters resulting from the sidewall roughness of TSVs under high-frequency conditions. By comparing the calculated results for different sidewall roughness with the outcomes from full-wave electromagnetic (EM) simulations, a high degree of consistency is maintained. Simultaneously, the parasitic parameters showcase systematic variations that correspond to changes in sidewall roughness. Our findings underscore that the adverse impact of TSVs' parasitic effects becomes more pronounced with heightened sidewall roughness. Importantly, the comparative analysis shows that the correction factor for inductance surpasses that of resistance, underscoring the significance of parasitic inductance. This finding attributes the primary source of parasitic effects to the parasitic inductance resulting from sidewall roughness. In addition, this study meticulously scrutinizes the experimental results, drawing comparisons against both calculated and simulated outcomes, resulting in a good degree of concurrence. This synchronization suggests that the proposed closed-form expressions adeptly capture the nuances of sidewall roughness in TSVs and thus prove highly suitable for scrutinizing a gamut of parasitic effects stemming from sidewall irregularities.