Thermomechanical Reliability of Through-Silicon Vias in 3D Interconnects

This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n-channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up mechanism of TSV with a 'nail head'. We first analyze the three-dimensional distribution of the thermal stresses near the TSV and the wafer surface. The stress characteristics are inherently 3D in nature with the near-surface stress distributions distinctly different from the 2D solution. The energy release rate for interfacial delamination of TSV is evaluated under both cooling and heating conditions, using an analytical solution for a steady-state crack growth as an upper bound and numerical solutions by finite element analysis (FEA) for more detailed calculations. Based on these results, we examine the piezoresistivity effect induced by the near surface stresses on the charge mobility for p-and n-channel MOSFET devices, including the study of the effect of TSV scaling on the keep-out zone for MOSFET devices. This is followed by analyzing the energy release rate for interfacial delamiantion for a fully filled TSV and the potential mechanisms for TSV pop-up due to interfacial fracture.