Diagnostic test pattern generation for sequential circuits

被引：23
|
作者：
Hartanto, I
Boppana, V
Patel, JH
Fuchs, WK
机构：
来源：
15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/VTEST.1997.600264
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.
引用
收藏
页码：196 / 202
页数：7
相关论文
共 50 条
  • [21] TEST-GENERATION FOR SEQUENTIAL-CIRCUITS
    MA, HKT
    DEVADAS, S
    NEWTON, AR
    SANGIOVANNIVINCENTELLI, A
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (10) : 1081 - 1093
  • [22] FsmTest: Functional test generation for sequential circuits
    Buonanno, G
    Fummi, F
    Sciuto, D
    Lombardi, F
    [J]. INTEGRATION-THE VLSI JOURNAL, 1996, 20 (03) : 303 - 325
  • [23] A new method of test generation for sequential circuits
    Hou, Yanli
    Zhao, Chunhui
    Liao, Yanping
    [J]. 2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING, 2006, : 2181 - 2185
  • [24] Deterministic built-in pattern generation for sequential circuits
    Iyengar, V
    Chakrabarty, K
    Murray, BT
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1999, 15 (1-2): : 97 - 114
  • [25] Deterministic Built-in Pattern Generation for Sequential Circuits
    Vikram Iyengar
    Krishnendu Chakrabarty
    Brian T. Murray
    [J]. Journal of Electronic Testing, 1999, 15 : 97 - 114
  • [26] A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. 2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, : 148 - 153
  • [27] Test generation for acyclic sequential circuits with hold registers
    Inoue, T
    Das, DK
    Sano, C
    Mihara, T
    Fujiwara, H
    [J]. ICCAD - 2000 : IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 2000, : 550 - 556
  • [28] MIX: A test generation system for synchronous sequential circuits
    Lin, XJ
    Pomeranz, I
    Reddy, SM
    [J]. ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 456 - 463
  • [29] Templates: A test generation procedure for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 74 - 79
  • [30] Modified test generation methods for synchronous sequential circuits
    Kemamalini, A.
    Seshasayanan, R.
    [J]. 2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
12345