Design and Implementation of Low Power Reservation Station of a 32-bit DLX-RISC processor

被引：0

作者：

Albuquerque, Nathaniel ^{[1
]}

Prakash, Kritika ^{[1
]}

Mehra, Anu ^{[1
]}

Gaur, Nidhi ^{[1
]}

机构：

[1] ASET Noida Amity Univ Uttar Pradesh, Dept Elect & Commun Engn, Noida, Uttar Pradesh, India

来源：

PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE (ICIS) | 2016年

关键词：

DLX-RISC processor; Tomasulo Algorithm; Out-of-Order Execution; Reservation station; Virtex-7; Kintex Ultrascale;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the implementation of a reservation station used in a 32-bit DLX RISC processor using Tomasulo algorithm on 20nm and 28nm FPGA boards and compares the results for power, delay and area. The algorithm is a computer architecture hardware algorithm for dynamic scheduling of the instructions that allows out-of-order execution. This design helps utilize multiple execution units more efficiently. The Reservation Station is the heart of Tomasulo algorithm and is responsible for out-of-order execution. The design is simulated and synthesized on Xilinx Vivado 2015.4 using VHDL and is implemented on Kintex Ultrascale and Virtex 7.

引用

页码：217 / 221

页数：5

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