Design of Low Power and Area Efficient Half Adder using Pass Transistor and Comparison of various Performance Parameters

被引：0

作者：

Kumar, Prashant ^{[1
]}

Bhandari, Navaneet Singh ^{[1
]}

Bhargav, Lokesh ^{[1
]}

Rathi, Rashmi ^{[1
]}

Yadav, S. C. ^{[1
]}

机构：

[1] Graph Era Univ, Dept Elect & Commun Engn, Dehra Dun 248002, Uttar Pradesh, India

来源：

2017 IEEE INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND AUTOMATION (ICCCA) | 2017年

关键词：

Half adder; CMOS NAND gate; CMOS transmission gate; 2:1 MUX; NMOS pass transistor logic (PTL);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The main objective of this paper is to design the low power consumption and less area occupied combinational circuit here we designed half adder circuit using three different logic styles: CMOS NAND gate logic, CMOS transmission gate logic, and NMOS pass transistor logic. All the circuits are simulated and compared by using Cadence Virtuoso IC 6.1.5, 180nm CMOS Technology with the supply voltage of 5V. In this paper we compare different performance parameters of these three logic styles, like power consumption, Number of transistors, propagation delay, rise time, fall time etc.

引用

页码：1477 / 1482

页数：6

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